The present invention relates to a scalar data arithmetic control system for a vector arithmetic processor in a data processing system.
FIG. 1 is a block diagram showing a conventional vector arithmetic processor in relation to a central processing unit (to be referred to as a CPU hereinafter). In FIG. 1, the vector arithmetic processor 100 includes an instruction register 6, a register file 4, an arithmetic unit 10, and a control unit 90. In operation an operand pointer is set based on the content of a vector instruction when the vector instruction is set in an instruction register 6 by the CPU and the vector arithmetic processor 100 initiates execution of the vector instruction. After the CPU 60 sets the instruction in the instruction register 6, an operand for performing the first cycle of the instruction is loaded. When the last operand is loaded, the CPU 60 loads the operand using a microinstruction for setting an operand counter. When the vector arithmetic processor 100 detects that the operand counter has been set, the operand is used to initiate an arithmetic operation.
When the designation for the vector arithmetic processor 100 is completed, the CPU 60 designates initiation of the second cycle. Even if the operand is a scalar operand, the same operand as in the first cycle is loaded. Upon completion of operand loading, the operand counter is set.
Even if a scalar operand is used, the same data is loaded every cycle. The difference between the scalar and vector operands is designated by a software instruction, and the CPU 60 determines the difference by detecting a designation bit
In the conventional vector arithmetic processor described above, the CPU must load the same operand in the vector arithmetic processor every vector instruction cycle, the number of steps in the microprogram is increased. The vector arithmetic processor must wait until the operand is input thereto. As a result, an operation speed cannot be increased.